1. Field
Exemplary embodiments of the present invention relate to a memory device.
2. Description of the Related Art
A memory device, such as Double Data Rate Synchronous DRAM (DDR SDRAM), has many memory cells. As the degree of integration of memory devices is increased, the number of memory cells also increases. The memory cells are regularly arranged to form an array, which is also called a memory cell block.
If memory cells of a memory device are defective, the memory device is discarded because it is unable to perform as required. As the process technology of memory devices advances, defects occur stochastically in only a small number of memory cells. If memory devices are discarded due to defective memory cells, product yield is negatively impacted. Therefore, memory devices include redundancy memory cells. If a defect occurs in the memory cells, they are replaced with the redundancy memory cells.
The operation of replacing defective memory cells with redundancy memory cells is called a “repair operation.” In particular, an operation for replacing a defective column (or bit line) with another column is called a “column repair operation.” A defective memory cell that needs to be replaced with a redundancy memory cell is called a “repair target memory cell.”
The memory cell structure of memory devices may be divided into folded bit line structures and open bit line structures, which have the following differences.
In the folded bit line structure, a bit line (e.g., a primary bit line) for driving data and a bit line (e.g., a secondary bit line) as a standard for an amplification operation are disposed in the same memory cell block on the basis of a bit line sense amplifier, which is disposed in the core region of a memory device. For this reason, the same noise is reflected in the primary bit line and the secondary bit line. These noises have mutual action so they are offset. The folded bit line structure supports stable operation when there is noise through this method. In the open bit line structure, a primary bit line and a secondary bit line are disposed in different memory cell blocks on the basis of a bit line sense amplifier. Accordingly, the open bit line structure is vulnerable to noise because the noise generated in the primary bit line is different than the noise generated in the secondary bit line.
FIG. 1 is a diagram illustrating part of the core region of a memory device having the open bit line structure, and FIG. 2 is a diagram illustrating a column control unit for controlling the column repair operation on the core region.
Referring to FIG. 1, the memory device may include memory blocks 110 and 120 and sense amplification units 130, 140, and 150. Each of the memory blocks 110 and 120 includes a plurality of word lines WL and a plurality of bit lines BL1/BLB1-BL3/BLB3 and may include redundancy bit lines RBL/RBLB for repairing defective bit lines. Each of the sense amplification units 130, 140, and 150 may include a plurality of sense amplifiers SA1 and SA4 for amplifying the data of corresponding bit lines BL1/BLB1-BL3/BLB3 or redundancy bit lines RBL/RBLB.
In the memory device of FIG. 1, column repairs may be independently performed on the memory block 110 and the memory block 120. For example, the bit lines BL1/BLB1 of the memory block 110 may be repaired by the redundancy bit lines RBL/RBLB of the memory block 110. The bit lines BL2/BLB2 of the memory block 120 may be replaced with the redundancy bit lines RBL/RBLB of the memory block 120 regardless of the column repair of the memory block 110.
A column control unit 210 may include fuse sets FS1 and FS2 for storing repair information for a column repair. The repair information may include the address of a column repaired by the redundancy bit lines RBL/RBLB, that is, a column address.
The column control unit 210 may select a column to be accessed in response to a column address CA and repair information R11 and R12. The column control unit 210 generates column selection signals Y1-Y3, and RY and may enable a column selection signal corresponding to a selected column. The column selection signal Y1 corresponds to the first sense amplifier SA1, and the column selection signal Y2 corresponds to the second sense amplifier SA2, and the column selection signal Y3 corresponds to the third sense amplifier SA3, and the column selection signal RY corresponds to the fourth sense amplifier SA4. The data of a bit line connected to a sense amplifier corresponding to an enabled column selection signal may be accessed.
A block selection signal XMAT<1:2> may be activated corresponding to a selected one of the memory blocks 110 and 120. The fuse set FS1 may store the repair information RI1 corresponding to the memory block 110. When the block selection signal XMAT<1> is enabled, the fuse set FS1 may output the stored repair information RI1. The fuse set FS2 may store the repair information RI2 corresponding to the memory block 120. When the block selection signal XMAT<2> is enabled, the fuse set FS2 may output the stored repair information RI2.
The column control unit 210 may enable one of the column selection signals Y1-Y3 that corresponds to the column address CA, but may enable the column selection signal RY if the column address CA and the repair information R11 and R12 of a selected fuse set are the same. For example, in the memory device of FIG. 1, it is described that an address corresponding to a column including the bit lines BL1/BLB1 has been stored in the fuse set FS1 and an address corresponding to a column including the bit lines BL2/BLB2 has been stored in the fuse set FS2. When the memory block 110 is selected, the block selection signal XMAT<1> is enabled and the repair information RI1 is outputted. If the column address CA and the repair information RI1 are different, the column control unit 210 may enable one of the column selection signals Y1-Y3 that corresponds to the column address CA. If the column address CA and the repair information RI1 are the same, the column control unit 210 may enable the column selection signal RY. Furthermore, when the memory block 120 is selected, the block selection signal XMAT<2> is enabled and the repair information RI2 is outputted. If the column address CA and the repair information RI2 are different, the column control unit 210 may enable one of the column selection signals Y1-Y3 that corresponds to the column address CA. If the column address CA and the repair information RI2 are the same, the column control unit 210 may enable the column selection signal RY.
The flexibility of a column repair is an important factor in increasing the yield of a memory device. Accordingly, research is being carried out on various methods for increasing the flexibility of a column repair.